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fn9140 rev 1.00 page 1 of 11 mar 2004 fn9140 rev 1.00 mar 2004 isl6608 synchronous rectified mosfet driver with pre-biased load startu p capability datasheet the isl6608 is a high frequen cy, mosfet driver optimized to drive two n-channel power mosfets in a synchronous- rectified buck converter topol ogy. this driver combined with an intersil hip63xx or is l65xx multi-phase buck pwm controller forms a complete single-stage core-voltage regulator solution with high ef ficiency performance at high switching frequency for ad vanced microprocessors. the ic is biased by a single low voltage supply (5v) and minimizes gate drive losses due to mosfet gate charge at high switching frequency applications. each driver is capable of driving a 3000pf load with a low propagation delay and less than 10ns transition time . this product implements bootstrapping on the up per gate with an in ternal bootstrap schottky diode, reducing impl ementation cost, complexity, and allowing the use of higher performance, cost effective n-channel mosfets. adaptive s hoot-through protection is integrated to prevent both mosfets from conducting simultaneously. the isl6608 features 4a sink c urrent for the lower gate driver, which is capable of ho lding the lower mosfet gate during the phase node rising edge to prevent shoot-through power loss caused by the high dv/dt of the phase node. the isl6608 also features a t hree-state pwm input which, working together wit h intersil multi-phas e pwm controllers, will prevent a negative transi ent on the outpu t voltage when the output is shut down. this f eature eliminates the schottky diode that is usually seen in a microprocessor power system for protecting the microprocessor from reversed output voltage events. a diode emulation feature is integrated in the isl6608 to enhance converter efficiency at light load conditions. diode emulation also prevents a negat ive transient when starting up with a pre-biased voltage on the out put. when diode emulation is enabled, the driver allows discontinuous conduction mode by detecting when the inductor current reaches zero and subsequentl y turns off the low side mosfet, which prevents the output from sinking current and producing a negative transi ent on a pre-bi ased output (see figures 6 and 7 on page 7). features ? dual mosfet drives for sy nchronous rectified bridge ? adaptive shoot-through protection ?0.5 ? on-resistance and 4a s ink current capability ? supports high switchin g frequency up to 2mhz - fast output rise/fall tim e and low propagation delay ? three-state pwm input for power stage shutdown ? internal bootstrap schottky diode ? low bias supply current (5v, 80a) ? diode emulation for enhanced light load efficiency and pre-biased startup applications ? vcc por (power-on-reset) feature integrated ? low three-state shutdown holdoff time (typically 160ns) ? pin-to-pin compatible with isl6605 ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile ? pb-free available as an option applications ? core voltage supplies for fpgas and powerpc microprocessors ? point-of-load modules wit h pre-biased start-up requirements ? high frequency and high cu rrent dc-dc converters related literature ? technical brief tb363 guidelines for handling and processing moisture sensit ive surface mount devices
isl6608 fn9140 rev 1.00 page 2 of 11 mar 2004 ordering information part number temp range (c) package pkg. dwg. # isl6608cb 0 to 70 8 ld soic m8.15 isl6608cb-t 8 ld soic tape and reel isl6608cr 0 to 70 8 ld 3x3 qfn l8.3x3 isl6608cr-t 8 ld 3x3 qfn tape and reel isl6608cbz (note) 0 to 70 8 ld soic (lead-free) m8.15 isl6608cbz-t 8 ld soic tape and reel (lead-free) isl6608crz (note) 0 to 70 8 ld 3x3 qfn (lead-free) l8.3x3 isl6608crz-t 8 ld 3x3 qfn tape and reel (lead-free) isl6608ib -40 to 85 8 ld soic m8.15 isl6608ib-t 8 ld soic tape and reel isl6608ir -40 to 85 8 ld 3x3 qfn l8.3x3 ISL6608IR-T 8 ld 3x3 qfn tape and reel isl6608ibz (note) -40 to 85 8 ld soic (lead-free) m8.15 isl6608ibz-t (note) 8 ld soic tape and reel (lead-free) isl6608irz (note) -40 to 85 8 ld 3x3 qfn (lead-free) l8.3x3 isl6608irz-t (note) 8 ld 3x3 qfn tape and reel (lead-free) note: intersil lead-free products employ special lead-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which is compatible with bo th snpb and lead-free soldering operatio ns. intersil lead-free products are msl classified at lead-free peak reflow temperatures that meet or exceed the lead-free requirem ents of ipc/jedec j std-020b. ordering information (continued) part number temp range (c) package pkg. dwg. # pinouts isl6608cb (soic) top view isl6608cr (3x3 qfn) top view ugate boot pwm gnd 1 2 3 4 8 7 6 5 phase fccm vcc lgate boot pwm vcc fccm lgate gnd ugate phase 7 8 4 3 1 2 6 5 6
isl6608 fn9140 rev 1.00 page 3 of 11 mar 2004 block diagram typical application - mu lti-phase conver ter using isl6608 gate drivers vcc pwm 10k control logic shoot- through protection boot ugate phase lgate gnd vcc fccm thermal pad (for qfn package only) isl6608 +5v boot ugate phase lgate pwm fccm vcc drive v bat +5v boot ugate phase lgate pwm v bat +v core pgood vid fs gnd isen2 isen1 pwm2 pwm1 vsen main fb vcc +5v comp isl6608 control vcc drive isl6608 +5v dacout fccm fccm thermal pad thermal pad
isl6608 fn9140 rev 1.00 page 4 of 11 mar 2004 ti absolute maximum ratings thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v boot voltage (v boot ). . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 22v phase voltage (v phase ) (note 1) . . . v boot - 7v to v boot + 0.3v input voltage (v de , v pwm ) . . . . . . . . . . . . . . . -0.3v to vcc + 0. 3v ugate. . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v to v boot + 0.3v lgate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . .- 40c to 125c recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . .-40 c to 85 c maximum operating junction temperatur e. . . . . . . . . . . . . . 125 c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v ? 10 % thermal resistance (typical, notes 2, 3, 4) ? ja (c/w) ? jc (c/w) soic package (note 2) . . . . . . . . . . . . 110 n/a qfn package (notes 3, 4). . . . . . . . . . 82 16 maximum junction temperat ure (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. the phase voltage is capable of withstanding -7v when the boo t pin is at gnd. 2. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 3. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 4. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. 5. guaranteed by design, not tested. electrical specifications recommended operating conditions, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc pwm pin floating, v vcc = 5v - 80 - ? a power-on reset (por) vcc rising - 3.40 4.00 v vcc falling t a = 0c to 70c 2.40 2.90 - v t a = -40c to 85c 2.175 2.90 - v hysteresis - 500 - mv bootstrap diode forward voltage v f v vcc = 5v, i f = 2ma 0.40 0.52 0.62 v pwm input input current i pwm v pwm = 5v - 250 - ? a v pwm = 0v - -250 - ? a pwm three-state rising threshold v vcc = 5v 0.80 1.00 1.20 v pwm three-state falling threshold v vcc = 5v, t a = 0c to 70c 3.40 3.65 3.90 v v vcc = 5v, t a = -40c to 85c 3.05 3.65 4.10 v v vcc = 5.5v - - 4.55 v three-state shutdown holdoff time t tsshd v vcc = 5v, t a = 0c to 70c 100 160 250 ns v vcc = 5v, t a = -40c to 85c 80 160 250 ns forced continuous conduction mode (fccm) input fccm low threshold 0.50 - - v fccm high threshold t a = 0c to 70c - - 2.00 v t a = -40c to 85c - - 2.05 v
isl6608 fn9140 rev 1.00 page 5 of 11 mar 2004 functional pin description ugate (pin 1 for soic-8, pin 8 for qfn) the ugate pin is the upper gate drive out put. connect to the gate of high-side pow er n-channel mosfet. boot (pin 2 for soic-8, pin 1 for qfn) boot is the floating bootstrap supply pin for the upper gate drive. connect the bootstrap ca pacitor between this pin and the phase pin. the bootstrap capa citor provides the charge to turn on the upper mosfet. se e the bootstrap diode and capacitor section under des cription for guidance in choosing the appropria te capacitor value. pwm (pin 3 for soic-8, pin 2 for qfn) the pwm signal is t he control input for t he driver. the pwm signal can enter three distinc t states during operation, see th e three-state pwm input section under description for further details. connect this pin to t he pwm output of t he controller. gnd (pin 4 for soic-8, pin 3 for qfn) gnd is the ground pin for the ic. lgate (pin 5 for soic-8, pin 4 for qfn) lgate is the lower gat e drive output. con nect to gate of the low-side power n-channel mosfet. vcc (pin 6 for soic-8, pin 5 for qfn) connect the vcc pin to a +5v bias supply. place a high quality bypass capacitor fro m this pin to gnd. fccm (pin 7 for soic-8, pin 6 for qfn) the fccm pin enables or disables diode emulation. when fccm is low, diode emulati on is allowed. otherwise, continuous conduction mode i s forced (fccm= forced continuous conduction mode). see the diode emulation section under description for more detail. phase (pin 8 for soic-8, pin 7 for qfn) connect the phase pin to the source of the upper mosfet and the drain of the lower mosfet. this p in provides a return path for the upper gate driver. thermal pad (in qfn only) the pcb thermal land desi gn for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). this combination of vias for vertical heat escape and buried planes for heat spreading allows the qfn to achieve its fu ll thermal potential. this pad should be grounded. refer to tb389 for design guidelines. switching time ugate rise time t ru v vcc = 5v, 3nf load - 8.0 - ns lgate rise time t rl v vcc = 5v, 3nf load - 8.0 - ns ugate fall time t fu v vcc = 5v, 3nf load - 8.0 - ns lgate fall time t fl v vcc = 5v, 3nf load - 4.0 - ns ugate turn-off propagation delay t pdlu v vcc = 5v, outputs unloaded - 35 - ns lgate turn-off propagation delay t pdll v vcc = 5v, outputs unloaded - 35 - ns ugate turn-on propagation delay t pdhu v vcc = 5v, outputs unloaded - 20 - ns lgate turn-on propagation delay t pdhl v vcc = 5v, outputs unloaded - 20 - ns ug/lg three-state propagation delay t pts v vcc = 5v, outputs unloaded - 35 - ns minimum lg on time in dcm (note 5) t lgmin - 400 - ns output upper drive source resistance r u 250ma source current - 1 2.5 ? upper driver source current (note 5) i u v ugate-phase = 2.5v - 2.00 - a upper drive sink resistance r u 250ma sink current - 1 2.5 ? upper driver sink current (note 5) i u v ugate-phase = 2.5v - 2.00 - a lower drive source resistance r l 250ma source current - 1 2.5 ? lower driver source current (note 5) i l v lgate = 2.5v - 2.00 - a lower drive sink resistance r l 250ma sink current - 0.5 1.0 ? lower driver sink current (note 5) i l v lgate = 2.5v - 4.00 - a electrical specifications recommended operating conditions, unless otherwise noted (continued) parameter symbol test conditions min typ max units
isl6608 fn9140 rev 1.00 page 6 of 11 mar 2004 description theory of operation designed for speed, the isl660 8 dual mosfet driver controls both high-side and low-side n-ch annel fets from one externally provided pwm signal. a rising edge on pwm initiates the turn-off of the lower mosfet (see figure 1, timing diagram). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the electrical specifications section. adaptive shoot-through ci rcuitry monitors the lgate voltage. when lgate has fallen below 1v, ugate is allowed to turn on. this prevents both the lower and upper mosfets from conducting simultaneou sly, or shoot-through. a falling transition on pwm indi cates the turn-off of the upper mosfet and the turn-on of t he lower mosfet. a short propagation delay [t pdlu ] is encountered be fore the upper gate begins to fall [t fu ]. the upper mosfet gate-to-source voltage is monitored, and the lower gate is allowed to rise aft er the upper mosfet gate-to-sour ce voltage drops below 1v. the lower gate then rises [t rl ], turning on the lower mosfet. this driver is optimized for co nverters with large step down compared to the upper mosfet because the lower mosfet conducts for a much longer time in a switching period. the lower gate driver is therefore sized much larger to meet this application requirement. the 0.5 ? on-resistance and 4a sin k current capability enable the lower gate driver to absorb t he current injected to the low er gate through the drain-to-gate capacitor of the lower mosfet and prevent a shoot through cau sed by the high dv/dt of the phase node. pwm ugate lgate t pdll t fl t pdhu t ru t pdlu t fu t pdhl t rl 1v 2.5v t ru t fu t fl 1v t pts t tsshd t tsshd t pts figure 1. timing diagram
isl6608 fn9140 rev 1.00 page 7 of 11 mar 2004 typical performance waveforms figure 2. load transient (0 to 30a , 3-phase) figure 3. load transi ent (30 to 0a, 3-phase) figure 4. dcm to ccm transition at no load figure 5. ccm to dcm tr ansition at no load figure 6. pre-biased startup in ccm mode (fccm = hi) figure 7. pre -biased startup in dcm mode (fccm = lo) inductor current vout inductor current vout
isl6608 fn9140 rev 1.00 page 8 of 11 mar 2004 diode emulation diode emulation allows for higher converter efficiency under light-load situations. with diode emulation active (fccm = lo), the isl6608 will detect the zero current crossing of the output inductor and turn off lgate. this ensures that discontinuous conduction mode (dcm) is achieved. this prevents the low side mosfet from sinking current, and no negative spike at the output is generated during pre-biased startup (see figure 7 on page 7). the lgate has a minimum on time of 400ns in dcm mode. diode emulation is asynchronous to the pwm signal. therefore, the isl6608 responds to the fccm input immediately after it changes state. refer to figures 2 to 7 on page 7 for details. intersil does not recommend d iode emulation used with the r ds(on) of the freewheeling mo sfet current sensing topology. the turn-off of the l ow side mosfet forces the forward current going through t he body diode of the mosfet. if the current sampling circuit of the controller is activated during the body diode conducti on, a diode voltage drop, instead of a much smaller mosfets r ds(on) voltage drop, is sampled. this will fal sely trigger the over current protection function of the controller. the isl6608 works with dcr, upper mosfet, or power resistor current sensing topologi es to start up from pre-biased load with no problem. three-state pwm input a unique feature of the isl6608 and other intersil drivers is t he addition of a shutdown window t o the pwm input. if the pwm signal enters and remains with in the shutdown window for a set holdoff time (typically 160ns), the outpu t drivers are disabled and both mosfet gates are pulled and held low. the shutdown state is removed wh en the pwm signal moves outside the shutdown window. ot herwise, the pwm rising and falling thresholds outlin ed in the electrical specifications dete rmine when the lowe r and upper gates are enabled. adaptive shoot-through protection both drivers incorporate adaptive shoot-through protection to prevent upper and lower m osfets from conducting simultaneously and shorting the input supply. this is accomplished by ensuring the fa lling gate has turned off one mosfet before the other i s allowed to turn on. during turn-off of the lower m osfet, the lgate voltage is monitored until it reaches a 1 v threshold, at which time the ugate is released to rise. adapt ive shoot-through circuitry monitors the upper mosfet gat e-to-source voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. internal bootstrap diode this driver features an intern al bootstrap schottky diode. simply adding an external ca pacitor across the boot and phase pins completes the boots trap circuit. the bootstrap capacitor must have a maximu m voltage rating above vcc + 5v and its capacitance value can be chosen from the following equation: where q g1 is the amount of gate c harge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot term is defined as the allowable droop in the rail of the upper drive. the previous relationship is illustrated in figure 8. as an example, suppose an upper mosfet has a gate charge, q gate , of 65nc at 5v and also assume the droop in the drive voltage over a pwm cycl e is 200mv. one will find that a bootstrap capacitanc e of at least 0.125 ? f is required. the next larger standard value capacitance is 0.15 ? f. a good quality ceramic capacitor is recommended. c boot q gate ? v boot ----------------------- - ? q gate q g1 vcc ? v gs1 ------------------------------- n q1 ? = figure 8. bootstrap capacitance vs boot ripple voltage 20nc ? v boot_cap (v) c boot_cap (f) 2.0 1.6 1.4 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc 1.2 1.8 5 0 n c
fn9140 rev 1.00 page 9 of 11 mar 2004 isl6608 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2003-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. power dissipation package power dissipation is mainly a function of the switching frequency and total gate char ge of the selected mosfets. calculating the power dissipati on in the driver for a desired application is critical to ensuring safe operation. exceeding t he maximum allowable power dissipation level will push the ic beyond the maximum recomm ended operating junction tem perature of 125 c. the maximum allowable ic power dissipation for the so-8 package is approximately 800mw. when designing the driver into an application, it is recommende d that the following calc ulation be performed to ensure safe operation at the desired frequency for the selected mosfets. the power dissipated by the driver is approximated as below and plotted as in figure 9. where f sw is the switching frequen cy of the pwm signal. v u and v l represent the upper and lower gate rail voltage. q u and q l are the upper and lower gat e charge determined by mosfet s election and any external capacitance added to the gate pins. the i ddq v cc product is the quiescent power of the driver and is typically negligible. layout consideration for heat spreading, place copper underneath the ic whether it has an exposed pad or not. t he copper area can be extended beyond the bottom area of the i c and/or connect ed to buried copper plane(s) with thermal vias . this combination of vias for vertical heat escape, exte nded copper plane, and buried planes for heat spreading allows t he ic to achieve its full thermal potential. place each channel power comp onent as close to each other as possible to reduce pcb coppe r losses and pcb parasitics: shortest distance between drains of upper fets and sources of lower fets; shorte st distance between drains of lower fets and the power ground. thus, smaller amplitudes of positive and negati ve ringing are on the switching edges of the phase node. however, som e space in between power components is required for good airflow. the gate traces from the drivers to the fets should be kept short and wide to reduce the inductance of the traces and promote clean drive signals. pf sw 1.5v u q u v l q l + ?? i ddq v cc + = figure 9. power dissipation vs frequency frequency (khz) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 power (mw) q u =50nc q l =50nc q u =50nc q l =100nc q u =100nc q l =200nc q u =20nc q l =50nc
isl6608 fn9140 rev 1.00 page 10 of 11 mar 2004 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l8.3x3 8 lead quad flat no-lead plastic package (compliant to jedec mo-220veec issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 3.00 bsc - d1 2.75 bsc 9 d2 0.25 1.10 1.25 7, 8 e 3.00 bsc - e1 2.75 bsc 9 e2 0.25 1.10 1.25 7, 8 e 0.65 bsc - k0.25 - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n82 nd 2 3 ne 2 3 p- -0.609 ? --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in mill imeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measure d between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provid ed to assist with pcb land patte rn design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & ? are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of t he package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
isl6608 fn9140 rev 1.00 page 11 of 11 mar 2004 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 ? 0 o 8 o 0 o 8 o - rev. 0 12/93

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